1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a non-volatile memory device comprising a bit line contact pad and a method for manufacturing the same.
2. Description of Related Art
In general, semiconductor memory devices include RAM devices and ROM devices. In RAM devices such as a DRAM (dynamic random access memory) and an SRAM (static random access memory), data is rapidly input/output to/from the RAM devices and the data is volatilized as time lapses. In contrast, ROM devices persistently maintain the data, but the data is slowly input/output to/from ROM devices. Examples of ROM devices include, for example, EEPROMs (electrically erasable and programmable ROMs) that are capable of electrically inputting/outputting data, and flash memory devices. A flash memory device is a type of advanced EEPROM, in which the input and output of data is electrically controlled by an F-N (Fowler-Nordheim) tunneling or a hot electron injection.
Flash memory devices generally include NAND-type flash memory devices and NOR-type flash memory devices. NAND-type flash memory devices comprise a plurality of cell transistors connected to each other in series for forming a unit string (which is connected between a bit line and a ground line in a row), and are used for high integration designs. In NOR-type flash memory devices, each cell transistor is connected between a bit line and a ground line in a row. NOR-type flash memory devices are used for high-speed operation. FIGS. 1A to 1C are sectional views of NAND-type flash memory devices manufactured according to a conventional method.
Referring to FIG. 1A, a tunnel oxide layer 12 (gate oxide layer) is formed on a semiconductor substrate 10 having a field area and an active area formed using a conventional isolation process. After depositing a first polysilicon layer 14 for a floating gate on the substrate, the first polysilicon layer 14 formed on the field area is etched using a photolithography process. Then, an ONO dielectric interlayer 16 and a second polysilicon layer 18 and tungsten silicide layer 19 (which comprise a control gate 20) are sequentially formed on the first polysilicon layer 14. Then, the tungsten silicide layer 19, the second polysilicon layer 18, the ONO dielectric interlayer 16 and the first polysilicon layer 14 are isotropically etched in sequence through a self-aligned etching process, thereby forming the gates of a memory cell transistor and a selective transistor.
After depositing an oxide film on the resulting structure to form a first insulating interlayer 22, the first insulating interlayer 22 is etched by using the photolithography process to form an opening 24 for a common source line (CSL). That is, the opening 24 exposes an active area formed between ground select lines (GSL).
After depositing a polysilicon layer in the opening 24 and on the first insulating interlayer 22, an etch-back process or a chemical mechanical polishing (CMP) process is performed to remove the polysilicon layer until the surface of the first insulating interlayer 22 is exposed. As a result, the common source line 26 is formed in the opening 24.
Continuing with reference to FIG. 1B, an oxide film is deposited on an entire surface of the resulting structure having the common source line 26 to form a second insulating interlayer 28. Then, the second insulating interlayer 28 is etched through a photolithography process to form a bit line contact hole 30 for connecting an active area to a bit line. That is, the bit line contact hole 30 exposes the active area formed between string select lines (SSL).
Referring to FIG. 1C, after depositing a polysilicon layer in the bit line contact hole 30 and on the second insulating interlayer 28, a bit line plug 32 for filling the bit line contact hole 30 is formed by removing the polysilicon layer until the surface of the second insulating interlayer 28 is exposed through an etch-back process or a CMP process. Then, a metal material, such as tungsten, is deposited on the bit line plug 32 and the second insulating interlayer 28. Thereafter, the metal material layer is patterned with a photolithography process, thereby forming a bit line 34 which contacts with the bit line plug 32.
There are disadvantages associated with the conventional method described above. For instance, a gap margin between the string select lines becomes insufficient for forming a bit line contact hole 30 (which connects an active area to a bit line), as the design rule is reduced. Further, a gap between the bit line contact holes is so densely formed that a bridge can be created between adjacent bit lines. Furthermore, a contact resistance is increased due to a fine bit line contact hole 30. There is a need, therefore, for a method for manufacturing a non-volatile device that can solve the above disadvantages.
It is an object of the present invention to provide a non-volatile memory device comprising a bit line contact hole formed on a bit line contact pad.
It is another object of the present invention to provide a method for manufacturing a non-volatile memory device in which a bit line contact hole is formed after forming a bit line contact pad so as to ensure a sufficient process margin for the bit line contact hole.
According to one aspect of the present invention, a non-volatile memory device comprises: a plurality of word lines formed on a semiconductor substrate having active areas, wherein the active areas are spaced by field areas and extend in a first direction while being repeatedly arranged in a second direction orthogonal to the first direction, wherein the plurality of word lines extend in the second direction while being repeatedly arranged in the first direction; string select lines which are adjacent to a first word line among the word lines and extend in the second direction and ground select lines which are adjacent to a last word line among the word lines and extend in the second direction; a first insulating interlayer formed on the word lines, the string select lines, the ground lines and the semiconductor substrate and comprising a first opening for partially exposing the active area formed between the ground select lines and a second opening for partially exposing the active area formed between the string select lines; a bit line contact pad formed in the second opening, a sidewall of the bit line contact pad comprising a negative slope in the first direction and a positive slope in the second direction; a hard mask layer pattern formed on the bit line contact pad and the first insulating interlayer and patterned in a same size as the active area; and a second insulating interlayer formed on the hard mask layer pattern and the first insulating interlayer and comprising a bit line contact hole for partially exposing the bit line contact pad.
According to another aspect of the present invention, a method for manufacturing a non-volatile memory device comprises the steps of: forming field areas and active areas on a semiconductor substrate such that the active areas are spaced by the field areas and extending in the a first direction while being repeatedly arranged in a second direction which is orthogonal to the first direction; forming a plurality of word lines, string select lines and ground select lines on the semiconductor substrate formed with the active areas, the word lines extending in the second direction while being repeatedly arranged in the first direction, the string select lines being adjacent to a first word line among the word lines and extending in the second direction, and the ground select lines being adjacent to a last word line among the word lines and extending in the second direction; forming a first insulating interlayer on the word lines, the string select lines, the ground select lines and the semiconductor substrate; etching the first insulating interlayer to form a first opening which partially exposes the active area formed between the ground select lines and extends in the second direction, and to form a second opening which partially exposes the active areas formed between the string select lines and extends in the second direction; forming a common source line in the first opening and a pad line in the second opening, simultaneously; forming a hard mask layer pattern on the common source line, the pad line, and the first insulating interlayer, the hard mask pattern being patterned in a same size as the active area; forming a bit line contact pad by slantingly etching the pad line using the hard mask layer pattern such that a sidewall of the bit line contact pad has a negative slope in the first direction and a positive slope in the second direction; forming a second insulating interlayer on the bit line contact pad and the first insulating interlayer; and etching the second insulating interlayer to form a bit line contact hole for partially exposing the bit line contact pad.
According to further aspect of the present invention, a method for manufacturing a non-volatile memory device comprises the steps of: forming field areas and active areas on a semiconductor substrate such that the active areas are spaced by the field areas and extending in the a first direction while being repeatedly arranged in a second direction which is orthogonal to the first direction; forming a plurality of word lines, string select lines and ground select lines on the semiconductor substrate formed with the active areas, the word lines extending in the second direction while being repeatedly arranged in the first direction, the string select lines being adjacent to a first word line among the word lines and extending in the second direction, and the ground select lines being adjacent to a last word line among the word lines and extending in the second direction; forming a first insulating interlayer on the word lines, the string select lines, the ground select lines and the semiconductor substrate; etching the first insulating interlayer to form a first opening which partially exposes the active area formed between the ground select lines and extends in the second direction, and to form a second opening which partially exposes the active areas formed between the string select lines and extends in the second direction; forming a common source line in the first opening and a pad line in the second opening, simultaneously; forming a hard mask layer pattern on the common source line, the pad line, and the first insulating interlayer, the hard mask pattern being patterned in a same size as the active area; forming a bit line contact pad by slantingly etching the pad line using the hard mask layer pattern such that a sidewall of the bit line contact pad has a negative slope in the first direction and a positive slope in the second direction; forming a second insulating interlayer on the bit line contact pad and the first insulating interlayer; forming a bit line insulating layer, which extends in the first direction while being repeatedly arranged in the second direction, on the second insulating interlayer; and forming a bit line contact hole by partially etching the second insulating interlayer formed on the bit line contact pad and simultaneously forming a metal contact hole by partially etching the second insulating interlayer formed on the common source line.
Preferably, when the common source line is formed, a pad line (which extends in the direction identical to the extending direction of the active areas) is formed on the bit line contact hole area. Then, the hard mask layer pattern having a pattern size identical to the size of the active area is formed on the pad line. The pad line is partially etched by using the hard mask layer pattern as an etching mask, so that the bit line contact pad is formed only on the active area to which the bit line is connected.
Advantageously, because the bit line contact hole is formed on the bit line contact pad, a misalign margin is sufficiently ensured when a photolithography process is performed for forming the bit line contact hole. In addition, when the photolithography process is performed, an etch margin is ensured by the stepped portion of the insulating interlayer.